Sign extension in VHDL

Okay, I am using VHDL at my new job, and haven't used it in years.  I was trying to sign extend basic logic circuits and it was driving me crazy.  Finally I found this, and it seems like it works:

Input signal to sign extend was
 
wimax_out       :in  std_logic_vector(15 downto 0); -- output of wimax modulator



in the architecture area...


-- sign extent input to 18-bits
wimax_sign_ext_18                             <= wimax_out(15) & wimax_out(15) & wimax_out;

-- sign extend to 48-bit C input
wimax_sign_ext_48(47 downto 16)     <= (others => wimax_out(15));
wimax_sign_ext_48(15 downto 0)       <= wimax_out;


So concating works (&) and the others => work, at least according to modelsim and the 'signed decimal' signals.  I am willing to bet other methods work, or perhaps work more properly, but I do not care

Verilog all the way

FPGA Timing

All right, I keep forgetting how FPGA timing works, so I'm writing it down here so I don't have to continue to search the internet

There are four main time periods we care about dealing with FPGA timing: Tclk, Tsu, Th, and Tco.

• Tclk is the period of the clock the registers in question are synchronous to.
• Tsu (Setup time) is the amount of time before the edge trigger of a register that the data must be settled on the input of the register
• Th (Hold time) is the amount of time after the edge trigger of a register that the data must remain stable on the input of the register
• Tco (Clock to output time)  is the amount of time from the edge trigger of the register to when the newly latched data is available as an output.

FPGA Timing Diagram Example

Here is an attached picture of three registers on the same clock, with the above time periods

From this we can see the amount of time a signal has to get from one register to another register in an FPGA is defined as

Time Skew = (Tclk - Tco - Tsu)

Skew is eaten into by delay that is a function of the speed of light, the trace material dielectric, the width of the trace, and probably something else I am forgetting.

These rules hold true in SDR or DDR -- we just care about the data with respect to the appropriate edge.  It can get more complicated with Center Aligned data or Edge Aligned, or dealing with external interfaces to the FPGA, but the main rule applies:

Data has to be there a certain amount of time before and after the sampling edge (Tsu and Th), and will take a certain amount of time before being available as an output (Tco), and is constrained by the clock period (Tclk) and the laws of physics.