Sign extension in VHDL

Okay, I am using VHDL at my new job, and haven't used it in years.  I was trying to sign extend basic logic circuits and it was driving me crazy.  Finally I found this, and it seems like it works:

Input signal to sign extend was
 
wimax_out       :in  std_logic_vector(15 downto 0); -- output of wimax modulator



in the architecture area...


-- sign extent input to 18-bits
wimax_sign_ext_18                             <= wimax_out(15) & wimax_out(15) & wimax_out;

-- sign extend to 48-bit C input
wimax_sign_ext_48(47 downto 16)     <= (others => wimax_out(15));
wimax_sign_ext_48(15 downto 0)       <= wimax_out;


So concating works (&) and the others => work, at least according to modelsim and the 'signed decimal' signals.  I am willing to bet other methods work, or perhaps work more properly, but I do not care

Verilog all the way